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Technology scaling results in a reduction in the soft error cross-section for individual memory and latch bits as well as that for individual logic gates. However, the proportion of logic soft error cross-section to latch soft error cross-section for a given circuit depends on several parameters, such as frequency of operation, logic circuit size, topology, etc. At multi-GHz range of frequencies, potentially the logic error cross-section will be comparable to the latch SE cross-section and could exceed it as well. However, increased leakage current and chip overheating ensured that designed chips never managed to reach their frequency potential. Thus, the scope of logic soft errors is unlikely to reach the levels predicted at the turn of the century. However, increased number of cells per IC has resulted in almost constant soft error FIT rates across technology nodes. The introduction of 3D FinFET structure does show a slight decrease in chip-level SE FIT rates at the 16-nm node. However, increase system-level functionalities negate all these trends by requiring increased number of ICs at each successive generation. As we scale down to sub-5-nm technology nodes with Gate-All-Around (GAA) transistors, while interesting charge collection mechanisms may emerge, it is likely that the soft error vulnerability will continue to scale down at the bit level primarily because of the ever-decreasing charge collection volume. However, with increasing system-level complexity, as we move towards data-intensive, edge computing applications, system level soft errors are not going away with scaling.