Publications
INVITED TALKS:
"Satellite-based Quantum Key Distribution", Keynote Speaker, International Conference on Security, Surveillance and Artificial Intelligence (ICSSAI) 2023, Kolkata, India.
"Single-Event Effects – Basic Mechanisms and Testing of Complex Devices", Short Course Speaker, European Data Handling & Data Processing Conference – EDHPC 2023, Juan-Les-Pins (French Riviera), France, 2023.
"The Radiation Environment in Space: An Introduction and its Impact on Space Exploration", Keynote Speaker, School of Physics, The University of Melbourne, Melbourne, Australia, 2023.
"Radiation tolerance for a space system", Invited Speaker, The Australian National University, Sydney, Australia, 2023.
"Soft Errors – from simple devices to complex systems", Tutorial Speaker, IEEE International Reliability Physics Symposium (IRPS) 2023, Monterey, CA, USA.
"Radiation Hardness Assurance and Tests for Space Missions – the Airbus way", Invited Speaker, G-RAD(NEXT) Workshop 2022.
"Total Ionizing Dose Effects in CMOS Devices", Short Course Speaker, School of Space Qualification 2023, University of Wollongong, Australia.
"EEE Reliability and Qualification for Space", Short Course Speaker, Space Qualification 2022, University of Wollongong, Australia.
"Single-Event Effects – Basic Mechanisms and Testing of Complex Devices", Short Course Speaker, IEEE Radiation Effects on Components and Systems (RADECS) 2021, Vienna, Austria.
"Radiation and Power- Key Constraints of Deep Space Exploration", Invited Speaker, University of Alabama Huntsville, Huntsville, AL, USA, July 2019.
"Radiation Hardness Assurance", Keynote speaker, RADHARD-Symposium 2018, Seibersdorf Laboratories , Austria, April 2018.
"Radiation Effects in Microelectronics", 2017 International Workshop on Reliability and Radiation Effects on Micro and Nano-electronic Devices, Chengdu, China. (invited)
“Radiation – A Key Driver for the ESA JUICE Mission”, Indian Institute of Engineering, Science and Technology, Shibpur, December 14, 2016
“Radiation Effects in Modern Microelectronics”, Institute of Microelectronics, Chinese Academy of Sciences, August 2015 (invited)
“Fault Tolerant Device Architectures for Space, Avionics and Critical Ground-based Systems”, Indian Institute of Technology, Gandhinagar, June 2, 2014
INVITED PUBLICATIONS:
M. Kuball, I. Chatterjee, et al., “Floating Body Effects in Carbon Doped GaN HEMTs”, 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, Blacksburg, Virginia, USA, Nov. 2015.
P. Moens, I. Chatterjee, et. al., “Intrinsic Reliability Assessment of 650V Rated AlGaN/GaN Based Power Devices: An Industry Perspective”, ECS Transactions, vol. 72, issue 4, pp. 65-76, May 2016.
JOURNAL PUBLICATIONS: (in chronological order)
H. Jiang, I. Chatterjee et al., "Power-Aware SE Analysis of Different FF Designs at the14/16-nm Bulk FinFET CMOS Technology Node", IEEE Transactions on Nuclear Science, Vol. 65, Issue 8, pp. 1866-1871, August 2018.
H. Zhang, I. Chatterjee et al., "Effects of TID Irradiation on SE Response of 14/16-nm Bulk FinFET FF Designs", IEEE Transactions on Nuclear Science, Vol. 65, Issue 8, pp. 1928-1934, August 2018..
M. J. Uren, I. Chatterjee, et. al., “Leaky Dielectric Model for the Suppression of Dynamic Ron Dispersion in Carbon Doped AlGaN/GaN HEMTs”, IEEE IEEE Transactions on Electron Devices, March 2017.
I. Chatterjee et al., “Lateral Charge Transport in Carbon-doped Buffer in AlGaN/GaN-on-Si HEMTs”, IEEE Transactions on Electron Devices, Vol. 64, Issue 3, pp. 977-983, January 2017.
B. Narasimham, I. Chatterjee et al., “Bias Dependence of Single-Event Upsets in 16-nm FinFET D-Flip-Flops”, IEEE Transactions on Nuclear Science, Vol. 62, Issue 6, pp. 2578-2584, Dec 2015.
B. L. Bhuva, I. Chatterjee et al., “Multi-Cell Soft Errors at Advanced Technology Nodes”, IEEE Transactions on Nuclear Science, Dec 2015, Vol. 62, Issue 6, pp. 2585-2591, Dec 2015.
I. Chatterjee et al., “Geometry Dependence of Total-Dose Effects in Bulk FinFETs“, IEEE Transactions on Nuclear Science, Vol. 61, Issue 6, pp. 2951-2958, Dec 2014.
I. Chatterjee et al., “Impact of Technology Scaling on SRAM Soft Error Rates“, IEEE Transactions on Nuclear Science, Vol. 61, Issue 6, pp. 3512-3518, Dec 2014.
N. N. Mahatme, I. Chatterjee et al, “Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors”, IEEE Transactions on Nuclear Science, Vol. 61, Issue 6, pp. 3274-3281, Dec 2014.
I. Chatterjee et al., “Bias Dependence of Total-Dose Effects in Bulk FinFETs“, IEEE Transactions on Nuclear Science, Vol. 60, Issue 6, pp. 4476-4482, Dec 2013.
N. N. Mahatme, I. Chatterjee et al “An efficient technique to select logic nodes for single event transient pulse-width reduction”, Elsevier Microelectronics Reliability, Volume: 53, Issue: 1, pp. 114–117, 2013.
N. N. Mahatme, I. Chatterjee et al, “Experimental Estimation of the Window of Vulnerability for Logic Circuits”, IEEE Transactions on Nuclear Science, vol. 60, Issue 4, pp. 2691-2696, June 2013.
I. Chatterjee et al., “Influence of User-Controlled Parameters in Alpha Particle-Induced Single-Event Error Rates in Commercial SRAM Cells”, IEEE Transactions on Nuclear Science, Vol. 59 Issue 4, pp. 872-879, Dec 2012.
I. Chatterjee et al., “Single-Event Charge Collection and Upset in 40 nm Dual- and Triple-Well Bulk CMOS SRAMs”, IEEE Transactions on Nuclear Science, Vol. 58, Issue 6, pp. 2761-2767, Dec 2011.
I. Chatterjee et al., “Cost Effective Implementation of a Phono Cardiogram Machine with PC Interface”, IETE Journal of Research, Vol. 54, Issue 6 (2008), p. 396-402.
CONFERENCE PAPERS/PRESENTATIONS: (in chronological order)
B. Ray, I. Chatterjee, et al., “RadiationTolerance of 3-D NAND Flash Based Neuromorphic Computing System”, IEEE International Reliability Physics Symposium (IRPS) 2020, Dallas, TX, USA
L. Xu, I. Chatterjee, et. al., "Single-Event Upset Responses of Dual-and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology", IEEE International Reliability Physics Symposium (IRPS) 2019, Monterey, CA, USA.
H. Zhang, I. Chatterjee et al., "Effects of TID Irradiation on SE Response of 14/16-nm Bulk FinFET FF Designs", IEEE Radiation Effects on Components and Systems (RADECS) 2017, Geneva, Switzerland.
H. Smith, I. Chatterjee et al., "Comparative Analysis of Unhardened and Hardened Flip-Flops for Low Power Applications in 14/16-nm Bulk FinFET CMOS Technology ", IEEE RADECS 2017, Geneva, Switzerland.
I. Chatterjee et al., “From MOSFETs to FinFETs – The Soft Error Story”. IEEE Nuclear and Space Radiation Effects Conference (NSREC) 2017, New Orleans, USA .
H. Zhang, I. Chatterjee et al., “SEU Responses of Dual- and Triple-Well Designs at the 16-nm FinFET Technology”, IEEE RADECS 2016, Bremen, Germany
H. Smith, I. Chatterjee et al., “Impact of Particle LET on Sequential Circuit SER for Advanced Technologies”, IEEE RADECS 2016, Bremen, Germany
W. Robinson, I. Chatterjee et al., “Design-Based Variability in Simulating Single Event Transients“, IEEE RADECS 2016, Bremen, Germany.
M. Power, I. Chatterjee, et al., “Reverse-biased induced mechanical stress in AlGaN/GaN power diodes”, International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2016.
S. Karboyan, I. Chatterjee et al., “Dynamic-Ron in Small and Large C-doped AlGaN/GaN-on-Si HEMTs”, International Conference on Compound Semiconductor Manufacturing Technology (CSMANTECH) 2016.
I. Chatterjee et al., “Impact of Buffer Charge on the Reliability of Carbon Doped AlGaN/GaN-on-Si HEMTs”, IEEE International Reliability Physics Symposium (IRPS) 2016.
N. N. Mahatme, I. Chatterjee et al., “Exploiting Low Power Circuit Topologies for Soft Error Mitigation”, IEEE IRPS 2016.
P. Moens, I. Chatterjee et al., “Intrinsic reliability assessment of 650V AlGaN/GaN HEMTs: on the impact of space charge limited current, and its implications for HTRB testing”, IEEE International Electron Device Meeting (IEDM) 2015.
M. Uren, I. Chatterjee et al., “Electron Trapping in GaN-on-Si Power HEMTs: Impact of Positive Substrate Bias”, International Conference on Nitrided Semiconductors (ICNS) 2015, Beijing, China.
B. Narasimham, I. Chatterjee et al., “Bias Dependence of Single-Event Upsets in 16-nm FinFET D-Flip-Flops”, IEEE NSREC 2015, Boston, MA, USA.
B. L. Bhuva, I. Chatterjee et al., “Multi-Cell Soft Errors at Advanced Technology Nodes”, IEEE NSREC 2015, Boston, MA, USA (Finalist for Outstanding Conference Paper Award)
N. Tam, I. Chatterjee et al., “Multi-Cell Soft Errors at the 16-nm FinFET Technology Node”, IEEE IRPS 2015, Monterey, CA, USA.
B. Narasimham, I. Chatterjee et al., “Influence of Supply Voltage on the Multi-Cell Upset Soft Error Sensitivity of Dual- and Triple-Well 28-nm CMOS SRAMs”, IEEE IRPS 2015, Monterey, CA, USA.
I. Chatterjee et al., “Effects of Well-Doping and Layout on Soft-Error Vulnerability for Advanced Technology SRAMs”, IEEE NSREC 2014, Paris, France.
I. Chatterjee et al., “Geometry Dependence of Total-Dose Effects in Bulk FinFETs”, IEEE NSREC 2014, Paris, France.
N. N. Mahatme, I. Chatterjee et al., “Power-Aware Mitigation of Combinational Logic Single Event Effects”, IEEE NSREC 2014, Paris, France.
N. N. Mahatme, I. Chatterjee et al., “Impact of Technology Scaling on the Combinational Logic Soft Error Rate”, IEEE IRPS 2014, Waikoloa, Hawaii, USA.
I. Chatterjee et al., “Bias Dependence of Total-Dose Effects in Triple-Well FinFETs”, IEEE NSREC 2013, San Francisco, CA, USA. (Finalist for Outstanding Conference Paper Award)
I. Chatterjee et al., “Length and Fin Number Dependence of Ionizing Radiation- Induced Degradation in Bulk nMOS FinFETs”, IEEE IRPS 2013, Monterey, CA, USA.
I. Chatterjee et al., Radiation Response of Backside Illuminated CMOS Imagers”, IEEE RADECS 2012, Biarritz, France.
I. Chatterjee et al., “Effects of Charge Confinement and Angular Strikes in 40 nm Dual- and Triple-Well Bulk CMOS SRAMs”, IEEE IRPS 2012, Anaheim, CA, USA.
I. Chatterjee et al., “Impact of Well Contacts on the Single Event Response of Radiation-Hardened 40 nm Flip-flops”, IEEE IRPS 2012, Anaheim, CA, USA.
I. Chatterjee et al., “Alpha Particle Induced Single-Event Error Rates and Scaling Trends in Commercial SRAM Cells”, IEEE RADECS 2011, Sevilla, Spain.
I. Chatterjee et al., “Single-Event Charge Collection and Upset in 40 nm Dual- and Triple-Well Bulk CMOS SRAMs”, IEEE NSREC 2011, Las Vegas, CA, USA.
N. N. Mahatme, I. Chatterjee et al., “Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies”, IEEE IRPS 2010, Anaheim, CA, USA.
N. Mahatme, I. Chatterjee et al., “An Efficient Technique to Select Logic Nodes for Single Event Transient Pulse Width Reduction”, IEEE RADECS 2010, Langenfeld, Austria.
I. Chatterjee et al., “Low Cost Implementation of Phonocardiogram Machine”, National Conference on New Generation Electronics 2008, Calcutta, India (Outstanding Conference Paper Award – Undergraduate)